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SYMMETRIC STACKING BINARY COUNTER

M.NAVIN KUMAR, A.S.DEVIKA, K.HARI KRISHNAN, S.JANE SELCIA.

Abstract
High efficient and fast addition of multiple operands is an essential process in any computational units. The power and
speed efficiency of multiplier circuits is one of critical importance in the overall performance of microcontrollers and
microprocessors. Multiplier circuits are an essential part of an arithmetic logic unit, or a digital signal processor
system for performing convolution, image processing, filtering, and other purposes. The binary multiplication of fixedpoint
numbers and integers ends up in partial products that is used to provide the ultimate product. Adding
those partial products dominates the power consumption and efficiency of the number. A new binary counter design
uses 3- bit stacking circuit, which groups all the 1 bits together, to combine pairs of 3- bit stacks into 6- bit stacks
through novel symmetric method has been proposed. The bit stacks square measure then reborn to binary counts,
producing 6:3 counter circuits with no xor gates on the critical path. This avoidance of xor gates results in faster
designs with efficient area and power utilization. Additionally, using the counters present in proposed system in
existing counter - based Wallace tree multiplier architectures reduces latency and power consumption for 128 and 64
- bit multipliers. We apply this Counter design in FIR filter Application

Key words: Stacking, Counter, Wallace, Multiplier, Filtering, Convolution.


 
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Pubmed Style

KUMAR M, A.S.DEVIKA , KRISHNAN K, SELCIA S. SYMMETRIC STACKING BINARY COUNTER. . 2019; 7(Supplement 1): 11-18. doi:10.31838/ijccts/07.SP01.03


Web Style

KUMAR M, A.S.DEVIKA , KRISHNAN K, SELCIA S. SYMMETRIC STACKING BINARY COUNTER. http://www.ijccts.org/?mno=302644473 [Access: October 17, 2019]. doi:10.31838/ijccts/07.SP01.03


AMA (American Medical Association) Style

KUMAR M, A.S.DEVIKA , KRISHNAN K, SELCIA S. SYMMETRIC STACKING BINARY COUNTER. . 2019; 7(Supplement 1): 11-18. doi:10.31838/ijccts/07.SP01.03



Vancouver/ICMJE Style

KUMAR M, A.S.DEVIKA , KRISHNAN K, SELCIA S. SYMMETRIC STACKING BINARY COUNTER. . (2019), [cited October 17, 2019]; 7(Supplement 1): 11-18. doi:10.31838/ijccts/07.SP01.03



Harvard Style

KUMAR, M., A.S.DEVIKA, ., KRISHNAN, . K. & SELCIA, . S. (2019) SYMMETRIC STACKING BINARY COUNTER. , 7 (Supplement 1), 11-18. doi:10.31838/ijccts/07.SP01.03



Turabian Style

KUMAR, M.NAVIN, A.S.DEVIKA, K.HARI KRISHNAN, and S.JANE SELCIA. 2019. SYMMETRIC STACKING BINARY COUNTER. International Journal of Communication and Computer Technologies, 7 (Supplement 1), 11-18. doi:10.31838/ijccts/07.SP01.03



Chicago Style

KUMAR, M.NAVIN, A.S.DEVIKA, K.HARI KRISHNAN, and S.JANE SELCIA. "SYMMETRIC STACKING BINARY COUNTER." International Journal of Communication and Computer Technologies 7 (2019), 11-18. doi:10.31838/ijccts/07.SP01.03



MLA (The Modern Language Association) Style

KUMAR, M.NAVIN, A.S.DEVIKA, K.HARI KRISHNAN, and S.JANE SELCIA. "SYMMETRIC STACKING BINARY COUNTER." International Journal of Communication and Computer Technologies 7.Supplement 1 (2019), 11-18. Print. doi:10.31838/ijccts/07.SP01.03



APA (American Psychological Association) Style

KUMAR, M., A.S.DEVIKA, ., KRISHNAN, . K. & SELCIA, . S. (2019) SYMMETRIC STACKING BINARY COUNTER. International Journal of Communication and Computer Technologies, 7 (Supplement 1), 11-18. doi:10.31838/ijccts/07.SP01.03