Abstract
This paper describes a CMOS current-steering digital-to-analog converter with a full-swing output signal. In a Wireless system the quality of the communication link is main criteria, for great distance transmission it is necessary to convert analog signal into digital signal at input side, same as convert digital signal to analog signal at output side. In the Existing DAC, 6 Binary inputs to 63 thermometer-coded (unary) outputs will use 6-input NOR and NAND logic gate, and the timing delay of these gates are very different. As the clock rate rising, it will cause error decoding problems.so we propose the 6 to 63 thermometer decoder by 2 section decoding. There is two 3 to 7 thermometer decoder for column and row decoder. This scheme reduces the error decoding problems. A new scheme of the quaternary driver and an output current cell composed of both nMOS and pMOS.The nMOS operates from the power supply to the half of the supply. The pMOS operates independently from the half of the supply to the ground voltage. Then, the final output voltage is obtained through a multiplexer that is driven by a quaternary driver that selects the optimized current cell. The circuit is simulated using 180nm Complementary Metal-oxide Semiconductor technology at a power supply voltage of 3.0 V on Tanner tool and the power consumption is about 17.8 mW. The proposed Current Steering Digital to Analog converter are schematic using Tanner S-EDIT and simulation of the proposed work is done using Tanner TEDIT. The waveform analysis is done using Tanner W-EDIT software